# set top variables
set synth_top top
set sim_top top_tb

# create project
create_project -force top work/top/ -part xc7a35tcpg236-1

# add source files
add_files -fileset sources_1 { \
    hdl/sec_counter/sec_counter.vhd \
    hdl/sec_counter/sec_counter_pkg.vhd \
    hdl/leds_controller/leds_controller.vhd \
    hdl/leds_controller/leds_controller_pkg.vhd \
    hdl/ssd_controller/ssd_controller.vhd \
    hdl/ssd_controller/ssd_controller_pkg.vhd \
    hdl/oled_controller/oled_controller.vhd \
    hdl/oled_controller/oled_controller_pkg.vhd \
    hdl/top/top.vhd \
    hdl/top/top_pkg.vhd \
    xdc/top.xdc \
}

# set project properties
set obj [get_projects top]
set_property "board_part_repo_paths" {/home/strlst/.Xilinx/Vivado/2021.2/xhub/board_store/xilinx_board_store} $obj
set_property "board_part" digilentinc.com:basys3:part0:1.1 $obj
set_property "simulator_language" "Mixed" $obj
set_property "target_language" "VHDL" $obj
set_property "file_type" {VHDL 2008} [get_files *.vhd]
update_compile_order -fileset sources_1
set_property top $synth_top [get_filesets sources_1]

# add sim files
add_files -fileset sim_1 { \
    tb/top/top_tb.vhd \
    wave/top_tb_behav.wcfg \
}

# set up sim properties
update_compile_order -fileset sim_1
set_property top $sim_top [get_filesets sim_1]

# set wavecfg
set_property xsim.view wave/top_tb_behav.wcfg [get_filesets sim_1]

# set ip cores
#set_property ip_repo_paths /home/strlst/hw/fpga/digilent/vivado-library-v2019.1-1 $obj
#update_ip_catalog